1. Field of the Invention
The present invention relates to a clock duty changing apparatus for regulating the duty ratio of the input clock signal having a duty ratio regulated to about 50% to a desired value.
2. Description of Related Art
A PLL (Phase Locked Loop) circuit disclosed in Japanese Unexamined Patent Application Publication No. 2000-59214 (hereinbelow, called patent document 1) includes a Voltage Controlled Oscillator (VCO) that includes an odd number of stages of inverters inside thereof. The VCO in the patent document 1 further includes a delay circuit connected between inverters forming the VCO and a delay control circuit controlling a delay time of the delay circuit in response to an external command. The PLL circuit disclosed in the patent document 1 changes the delay time of the delay circuit according to the external command to change duty ratio of the clock signal generated by the VCO.
Japanese Unexamined Patent Application Publication No. 2004-348573 (hereinbelow, called patent document 2) discloses a clock generation circuit including a PLL circuit and a delay circuit connected to an output of the PLL circuit. The clock generation circuit disclosed in the patent document 2 is able to change duty ratio of a clock signal output from the PLL by employing a delay signal generated by delaying the clock signal output from the PLL circuit as a control signal. Further, the patent document 2 discloses regulating delay amount of the delay circuit included in the clock generation circuit to a desired duty ratio by controlling the delay amount in multiple stages using a multi-value delay control signal.
Further, Japanese Unexamined Patent Application Publication No. 2003-243973 (hereinbelow, called patent document 3) discloses a duty regulation circuit for making the duty ratio of the clock signal whose duty ratio is not 50% close to 50%. To be more specific, the duty regulation circuit disclosed in the patent document 3 employs the delay signal generated by delaying the input clock signal by a delay line as the control signal in order to change the duty ratio of the input clock signal. Further, the duty regulation circuit disclosed in the patent document 3 detects whether the duty ratio of the output clock signal whose duty ratio is regulated is the desired duty ratio of 50%. The duty regulation circuit disclosed in the patent document 3 changes the delay amount of the delay line according to the detection result to regulate the duty ratio of the output clock signal. However, the duty regulation circuit disclosed in the patent document 3 does not change the duty ratio of the input clock signal to the value other than 50%. Further, the duty regulation circuit disclosed in the patent document 3 is not configured to change the delay amount of the delay line according to the control signal from an external device.
I have now discovered that there are problems as follows in the techniques disclosed in the patent documents 1 and 2. In the technique disclosed in the patent document 1, which is the technique connecting the delay circuit to the VCO included in the PLL circuit to change the duty ratio of the clock signal in response to the external command, is only effective when the VCO is configured by the odd number of stages of inverters. Moreover, the delay circuit for changing the duty ratio is provided inside the PLL circuit, which requires modifying a core in order to apply this technique to the PLL (PLL core) which is produced as an IP core. Further, when the PLL core is formed as black box, it is difficult to change the duty ratio of the clock signal generated by the PLL by employing the technique disclosed in the patent document 1.
In the clock generation circuit disclosed in the patent document 2, the circuit including the delay circuit is connected to the output of the PLL circuit and regulates the duty ratio of the clock signal generated by the PLL circuit. However, even when the regulation is carried out to obtain the clock signal having the desired duty ratio by the control signal from the external device, the duty ratio of the clock signal that is actually output may not be the desired duty ratio due to tolerance in a production process of the delay circuit or the like. The patent document 2 does not disclose the technique for attaining the desired duty ratio by compensating the fluctuation of the duty ratio due to the production tolerance or the like.